It is known that permanent connections provide a high reproducibility, quality and reliability of an electronic equipment. In the microelectronics equipment designs, most of permanent connections are formed by joining pairs of contact into contact nodes during producing operations (soldering, welding, spraying, galvanic build-up etc.)
At the moment the requirements to provide a speed performance and miniaturization become increasingly crucial in creating and manufacturing the modern electronic equipment.
The promising direction of development is to create the equipment on the base of housing-less components, including LSIC, in the form of multichip modules which are characterized by a high component mounting density, interconnection topology optimization and increase of the speed performance of the MCM equipment.
In that connection, efforts of many microelectronics equipment designers' are directed to develop multilayered connection structures with high interconnection density with a reliable contacting of conductors being in adjacent connection layers as well as methods for joining housing-less components, and first of all, multi-lead LSIC chips to mounting contacts of multilayered connection structure as a part of the MCM.
One of the almost insurmountable obstacle for obtaining the high interconnection density in the MCM multilayered substrates is in the forming of a great number (several thousands) of reliable contact nodes having identical features and connecting the conductors from different connection layers into single topology of the multilayered structure.
Other, no less hard problem is to joining reliably and reproducibly the contact pads of LSIC chips to respective contact pads of the multilayered MCM structure.
The chips of modern LSICs (for example, Pentium chips) have dimensions exceeding 1 sq. cm, more than 400 contact pads and clock operating frequencies greater than 400 MHz. An assembling of such chips into a single MCM node with chips of Cash memory is a very actual problem. Actuality of this problem would only increase with developing the microelectronics equipment manufacture and LSIC element base.
The contact node as a component of the MCM multilayered connection structure could be a combination of at least two metallized contacts, for example, in the form of coaxially jointed metallized holes made in two adjacent connection layers interconnected electrically and mechanically.
The contact node for mounting a LSIC chip as a component of the MCM also could be represented by a combination of two aligned contacts one of which being on a chip surface and a respective contact being on the MCM mounting layer. The contacts are interconnected by a conductive structure, which could be, depending on forming method, as follows:                a wire welded to the contacts;        a jumper formed on the dielectric material film and welded to the contacts;        a tinned protrusion previously formed on one contact and soldered to another one.        
Variety contact node designs for mounting the chips could be divided into following types (Ma3yp A.  p. πpoeccI cBapK  πak B πpo3BocTBe πoyπpoBoHKoBIx πpopoB. M.: “Pao  cB3”, 1991. C. 38-39—Mazur A. et al. Welding and soldering processes in manufacturing the semiconductor devices. Moscow: “Radio and Sviaz”, 1991. Pp. 38-39).
Type 1 is characterized by an arrangement of contacts being connected (one contact on the chip surface, other one on the mounting surface) in different parallel planes. In so doing, the contacts are faced by working surfaces to one side and connected by extended intermediate elements, for example, by wire welded to the contacts.
Type 2 is characterized by an arrangement of contacts in one plane. The contacts are also connected by extended intermediate elements which are beam connectors.
Type 3 is similar to Type 1, the contact pads are also arranged in the parallel planes, but faced to each other with their working surfaces. The intermediate element of extended type is a beam on the polyimide film.
It is necessary to note two main disadvantages of above mentioned types of the contact nodes:                a utilization of defect-forming producing operations (welding);        a non-group character of main assembling operations (forming every contact node individually and sequentially, with two weldings for every contact node).        
Type 4 is similar to Type 3, but the contacts are mutually aligned, whereby the intermediate element has a minimal extension and is made in the form of protrusion having the bump or ball form previously formed on the chip contact. A connection of the contacts is performed by soldering.
An advantage of the Type 4 contact node is a group character of preliminary and assembling operations (assembling all contact nodes simultaneously).
Main disadvantages are as follows:                the impossibility to perform direct visual and electrical control of process and results of the contact node assembling due to the fact that the chip turned by its “face” (and all contact pads) to the substrate covers all aligned respective contact pads on the substrate;        the lack of natural exit for working waste of assembling (for example, the flux) from a very narrow gap between the substrate and chip due to substantial capillary forces in this gap;        the lack of effective methods for withdrawing the working waste of assembling from the gap between the substrate and chip, which leads to degradation phenomena in the chip during its exploitation and to decreasing in a reliability of the chip operation.        
The contact node used in assembling the polyimide connection layers into multilayered operation plate is known, consisting of two contacts in adjacent layers which contacts are made in the form of metallized holes which with form, together with metallized holes of other layers, the matrix of through channels piercing all plate layers throughout. After coaxial alignment and jointing, all pairs of contact through holes are interconnected by the method of vacuum soldering (πaHoB E.H. OcoeHHocT copK cπea3poBaHHIx C Ha a3oBIx MaTpHIx KpcTaax. M.: “BIcaKoa”, 1990. C. 33-34. Panov E. N. The peculiarities of assembling the specialized LSIC on basic matrix chips. Moscow: “Vysshaya Shkola”, 1990. Pp. 33-34).
However, such construction of the contact node leads to greater expenditure of usable plate area for through channel matrix, which decrease sufficiently the interconnection spreading density, lead to increase number of plate layers and number of soldered joints, i.e. decrease the manufacture adaptability of the plate and increase its cost while degrading reliability characteristics.
The closest to the present invention by the technical essence and achieved result during its utilization is the contact node including two contacts, one of which contacts is made in the form of metallized tinned protrusion having a bump or ball form on a contact pad of LSIC chip, and the second contact is in the form of metallized contact pad coupled with conductors on a mounting surface of a connection structure. After their aligning, the contacts are interconnected electrically and mechanically by means of a conductive binding structure (MopKoB O.C. TexHooπ πoyπpoBoHKoBIx πpopoB  3eMKpoeKTpoHK. M.: “BIca Koa”, 1990. C. 38-40—Moryakov O. S. Technology of semiconductor devices and microelectronics items. Moscow: “Vysshaya Shkola”, 1990. Pp. 38-40).
Such contact node design is characterized by:                great technological difficulties in forming protrusions of complex form and structure and uniform by height on the contact pads of the LSIC chips having a multiplicity of leads (500 contacts and over);        utilizing the defect-forming producing operations and processes in forming 3D protrusions on the LSIC contact pads;        the impossibility to perform direct visual and electrical inspection of the process and results in assembling a great number of contact nodes placed in a very narrow gap between the substrate and the chip;        great difficulties in withdrawing the working waste, being formed during the process of soldering the contact nodes, from the gap between the chip and substrate, which effects negatively on the reliability of connections.        